TI公司的TMS320VC5505是基于TMS320C55xDSPCPU核的定點DSP,它的C55x™DSP架構可得到高性能和低功耗特性,CPU支持內部總線架構,包括一條可編程總線,一條321位數(shù)據(jù)總總線和兩條16位數(shù)據(jù)讀總線,兩條數(shù)據(jù)寫總線和專門用于外設和DMA的其它總線.TMS320VC5505還包括4個DMA控制器,每個四路.時鐘為60MHz或100MHz,指令周期為16.67ns或10ns.主要用于無線音頻設備,回聲消除耳機,手提媒體設備,視頻,工業(yè)控制,指紋生物學和SDR.本文介紹了TMS32
TI公司的TMS320VC5505是基于TMS320C55x
DSPCPU核的定點DSP,它的C55x™ DSP架構可得到高性能和低功耗特性,CPU支持內部總線架構,包括一條可編程總線,一條
321位數(shù)據(jù)總總線和兩條
16位數(shù)據(jù)讀總線,兩條數(shù)據(jù)寫總線和專門用于外設和
DMA的
其它總線. TMS320VC5505還包括4個DMA控制器,每個四路.時鐘為60MHz或
100MHz,指令周期為16.67ns或10ns.主要用于無線音頻設備,回聲消除耳機,手提媒體設備,視頻,工業(yè)控制,指紋生物學和
SDR.本文介紹了TMS320VC5505的主要特性和方框圖以及采用TMS320VC5505的脈沖血氧計方框圖, VC5505
EVM評估板主要特性, 脈沖血氧計前端方框圖和電路圖以及所用材料清單.
Pulse Oximeter Implementati
onon the TMS320VC5505 DSP Med
ical Development Kit
Pulse oximeters me
asure arterial blood oxygen saturation by sensing absorption pro
perties of deoxygenated and oxygenated hemoglobin using various wavelengths of light. A basic meter is comprised of a sensing probe attached to a patients earlobe, toe, finger, or other body locations, and data acquisition system for the calculation and display of oxygen saturation level, heart rate, and blood flow.
圖1.脈沖血氧計方框圖
The TMS320VC5505 is a member of TIs TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-
powerapplications.
The TMS320VC5505 fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The TMS320VC5505 also includes four DMA controllers, each with 4 channels, providing data movements for 16-independent channel contexts without CPU intervention. Each DMA controller
canperform one 32-bit data transfer per cycle, in parallel and independent of